Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage node, such as floating gates or trapping layers or other physical phenomena, determine the data state of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a logical column of memory cells is coupled in parallel with each memory cell coupled to a data line, such as those typically referred to as bit lines. In NAND flash architecture, a column of memory cells is coupled in series with only the first memory cell of the column coupled to a bit line.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a very cost effective non-volatile memory.
Multilevel cells can take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific threshold voltage (Vt) range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell and the stability of the assigned voltage ranges during the lifetime operation of the memory cell.
For example, a cell may be assigned four different voltage ranges of 200 mV for each range. Typically, a dead space of 0.2V to 0.4V is between each range to keep the ranges from overlapping. If the voltage stored on the cell is within the first range, the cell is storing a logical 11 state and is typically considered the erased state of the cell. If the voltage is within the second range, the cell is storing a logical 01 state. This continues for as many ranges that are used for the cell provided these voltage ranges remain stable during the lifetime operation of the memory cell.
Since two or more states are stored in each MLC, the width of each of the voltage ranges for each state can be very important. The width is related to many variables in the operation of a memory circuit. For example, a cell could be verified at one temperature and read at a different temperature. The circuitry that determines if the cell is erased or programmed to the correct Vt range has to make that determination. That circuitry has some of its characteristics influenced by temperature. A Vt window is a sum of all of these types of differences, translating into a shift in the perceived window of the Vt. In order for the window to operate, the width of the four states plus a margin between each state should amount to the available window.
MLC memories often use a larger number of Vt ranges than are required to store the bits of data to be stored. For example, 16 ranges may be used in a MLC between −2 volts and +3 volts, to allow for more ranges to be used to program the bits of data that are to be programmed in the memory.
In MLC memories using a number of voltage ranges (also referred to as levels), cells to be programmed to lower levels, for example those cells to be programmed to levels 0-7 of a 16 level memory, are subjected during normal programming sequences to potentially large amounts of disturb due to the high voltages used for programming cells to higher levels such as levels 8-15 of a 16 level memory.
In MLC memories using a number of levels, cells to be programmed to lower levels, especially those cells to be programmed to levels 0-7 of a 16 level memory, are subject to disturbance from programming of upper level cells. For example, cells at level 0 program typically at a control gate voltage of approximately 13-15 volts, whereas the cells at level 15 program typically at a control gate voltage of approximately 22-24 volts, depending upon whether they are fast or slow programming cells. When cells are programmed in a typical programming sequence of applying a series of programming pulses beginning at 12 volts and ending at 24 volts, level 0 cells program first since they program at the lower levels, and are then inhibited because they have reached their level. One problem is that level 0 cells are inhibited, and during programming of the rest of the cells at higher voltages, the level 0 cells are subject to program disturb. Level 0 cells are disturbed more than level 15 cells, since they see a greater number of voltage pulses higher than their level, even if they are inhibited.
For reasons such as those stated above, and for other reasons, such as those stated below, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for, among other things, reducing disturbance of cells programmed to lower levels, while maintaining programming speed.